Introduction

In recent digital signal processing algorithms and various other applications, multipliers are used in tremendous amounts. With advancements in technology and also increased demand of high speed with less area required, many researchers have tried and are also in present designing multipliers. Their aims are to have high speed, low power consumption, regularity of layout and regularity and so with it also less area or even it can have combination of both in one multiplier which can make them suitable for various high speed, low power and compact VLSI design implementations

As we know that addition and multiplication of two binary numbers is one the fundamental and most rudimentary arithmetic operations in the high performance systems. Most common multiplication method is the ‘add and shift’ mechanism. According to the statistics nearly 70% of instructions processed by microprocessors and also most digital signal processing algorithms perform addition and multiplication. So, it can be said that multipliers are key components of many high-performance systems. They can be found in FIR filters, microprocessors, digital signal processors, etc. Using them efficiently reduces the execution time. This is the main reason why we have a requirement of high-speed multipliers. Also we have a demand for high-speed processing has been increasing as more and more use of computers and other signal processing applications have increased tremendously. Having a low power consumption is one of an important characteristics taken in consideration while designing multipliers. To reduce significant power consumption, it is good to reduce the number of operations thereby reducing dynamic power which is a major part of total power consumption, due to the above reasons the need of high speed along with low power multipliers has increased drastically. Designer mainly puts emphasis on high speed and low power efficient circuit design. The aim of a good multiplier is to be physically packed together,and should provide a high speed and also must have a  low power consumption unit.

For parallel multipliers, the number of partial products computed at an instance is considered as the main parameter that determines the performance of the multiplier. For reducing these partial products, the Modified Booth algorithm is one the most widely used algorithms. For further optimization and improved speed Wallace Tree algorithm can be considered an efficient way which works by reducing the number of sequential adding stages. On combining both the above algorithms we can have advantages of both in one multiplier. But this comes with a drawback, with increasing parallelism the number of shifts between partial products will also rise which may lead to reduced speed, inflation in silicon area because of irregularity of structure and also higher power consumption due to increased power consumption due to this it would result in complex routing too. The ‘serial-parallel’ multipliers on the other hand compromise speed for gaining better performance for area and power consumption. Selection of these parallel or serial multipliers highly depends on the nature of application which we require. So, the following blog will introduce you with different multiplier algorithms and then compare them on the basis of different parameters i.e. speed, area, power and combination of these metrics.

Fig. 1: Classification of multipliers

Author: Utkarsh Jakate, Chinmay Jangle, Dhananjay Joijode, Sameer Karoshi

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