Braun Multiplier

In Braun multiplier, the partial products are first computed in parallel then collected through a cascade of different types of adders. It consists of an array of AND gates and adders arranged in an iterative structure which doesn’t require any logic registers. So it is a type of parallel array multiplier.

4-Bit Braun Multiplier:

4 bit Braun multiplier contains two inputs of 4-bit i.e., A0-A3 and B0-B3 and the output is 8-bit which is P0-P8. Fig 1 gives the circuit of 4-bit Braun multiplier. For layout, to make the connections easier, an AND gate and a Full adder is taken as one unit. 9 of such units are placed accordingly in the layout. The top layer consists of 4 AND gates, high is taken as one instance. The remaining 3 and gates to the extreme left  is  taken as one more instance.

Fig. 1: 4x4 Braun Multiplier  

8-Bit Braun Multiplier:

The circuit used in the 4-bit Braun multiplier is taken as the instance for the schematic implementation of the 8-bit Braun multiplier. Here there are two inputs each of 8-bit which is A0-A7 and B0-B7. The outputs are P0-P15 which is 16-bit.  For layout, to make the connections easier, an AND gate and a Full adder is taken as one unit. 36 of such units are placed accordingly in the layout. The top layer consists of 8 AND gates, which is taken as one instance. The remaining 6 and gates to the extreme left is taken as one more instance.

Fig. 2: 8x8 Braun Multiplier

16-Bit Braun Multiplier:

The circuit used in the 4-bit Braun multiplier is taken as the instance for the schematic implementation of the 16-bit Braun multiplier. Here there are two inputs each of 16-bit which is A0-A15 and B0-B15. The outputs are P0-P31 which is 32-bit. For layout, to make the connections easier, an AND gate and a Full adder is taken as one unit. 225 of such units are placed accordingly in the layout. The top layer consists of 16 AND gates, which is taken as four instance of 4 each. The remaining 12 AND gates to the extreme left is taken as four more instances of 3 each.

Fig. 3: 16x16-bit Pyramidal adder

Author: Sameer Karoshi